Dr. Veena S. Chakravarthi is a VLSI system architect and a Director with LeadSOC Technologies, Bangalore. She holds a doctoral degree from Bangalore University for her research on "Generalized power optimization design methodologies for application-specific integrated circuits" and is an alumnus of the Indian Institute of Management, Bangalore. Over the years, Dr. Chakravarthi has established herself as a leading system architect of communications, optical, and wireless semiconductor solutions with a wide range of expertise in high-performance and low-power systems on chips (SoCs). She started her career at ITI Limited, a premier public sector company, and later joined MindTree Consulting, where she developed wireless IPs in Bluetooth and WLAN technologies. Dr. Chakravarthi has worked for Centillium India Limited and Transwitch India Limited, where she was involved in developing Gigabit EPON chipsets and communication processors. She has been a technical consultant for the companies Ikanos Communications and Periera Ventures and vice president of Asarva Chips & Technologies. She is also a co-founder and advisor for Sensesemi Technologies, Bangalore. In the recent past, she was in the Accelerated Customer Experience Group with Synopsys, where she developed a certification course for five tracks of VLSI design and trained customers on advanced Synopsys tools. Dr. Chakravarthi has filed six patents and holds two patents in the United States and India for inventions in VLSI and IoMT solutions for Sensesemi and BNMIT. She is the author of the books A Practical Approach to VLSI System on Chip (SoC) Design: A Comprehensive Guide, Second Edition (Springer, 2022), Internet of Things and M2M Communication Technologies (Springer, 2021), SoC Physical Design: A Comprehensive Guide (Springer, 2022) and System on Chip (SOC) Architecture: A Practical Approach (Springer, 2023). Dr. Chakravarthi has authored numerous papers on VLSI and healthcare and has held chair and vice-chair positions with the IEEE Nanotechnology Council (NTC), Bangalore Section. She is a senior IEEE member.

Dr. Shivananda R. Koteshwar (Shivoo) has over 27 years of experience in the semiconductor industry and is the EDAG Site Head with Synopsys India. He has been a catalyst and driver for many incubators and accelerators. He is the founding Trustee of the Belakoo Trust, which focuses on rural education, skill development, and experiential learning, and a co-trustee of Aurinko Trust, whose flagship product is The Aurinko Academy, a progressive K12 school in Bangalore with focused programs in all new-age careers. He received a doctorate in Education Management and is an alumnus of IIM, Bangalore, and has a Postgraduate Diploma in Innovation and Design Thinking, a collaborative program by MIT Sloan, Columbia Business School, and Tuck University. He has a Master's Degree in Electrical Engineering from OGI School of Science and Engineering and a BTech in Electronics and Communication Engineering from Mysore University. He is the co-author of the books System on Chip (SOC) Architecture: A Practical Approach (Springer, 2023) and SOC Physical Design: A Comprehensive Guide (Springer, 2022), and has authored three other books: 50 Shades of Life, 50 Colours of Love, and English Kaliyiri. He actively mentors start-ups catering to EdTech and the learning space.

Provides a comprehensive overview of the skills required for complex SoC design and development;

Examines SOC design challenges in nanotechnology scales;

Offers readers professional "tricks" to using tools for optimal design runs.

Introduction.- SoC Physical Design Flow and Algorithms.- Physical Design Floor Plan and Placement.- Clock, Reset, and HFN.- Physical Design Routing.- Physical Design Verification.